LA-LATTICEXP2 Datasheet, PDF (20/83 Pages) Lattice Semiconductor – LA-LatticeXP2 Family Data Sheet

Lattice Semiconductor
Architecture
LA-LatticeXP2 Family Data Sheet
EBR memory supports two forms of write behavior for single port or dual port operation:
1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This
mode is supported for all data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively. GSRN, the global reset signal, resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2-17.
Figure 2-17. Memory Core Reset
Memory Core
Q D ^SET
LCLR
Port A[17:0]
RSTA
Output Data
Latches
Q D ^SET
LCLR
Port B[17:0]
RSTB
GSRN
Programmable Disable
For further information on the sysMEM EBR block, please see TN1137, LatticeXP2 Memory Usage Guide.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the low-to-high transition of the reset signal, as shown in Figure 2-18.
The GSR input to the EBR is always asynchronous.
Figure 2-18. EBR Asynchronous Reset (Including GSR) Timing Diagram
Reset
Clock
Clock
Enable
2-17