GAL22V10D-15LPN Datasheet, PDF (16/23 Pages) Lattice Semiconductor – Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Specifications GAL22V10
Power-Up Reset
Vcc
Vcc (min.)
CLK
t su
t wl
INTERNAL REGISTER
Q - OUTPUT
t pr
Internal Register
Reset to Logic "0"
S _{ACTIVE LOW}
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
E _{D ACTIVE HIGH}
OUTPUT REGISTER
Device Pin
Reset to Logic "0"
IC ^E _{Circuitry within the GAL22V10 provides a reset signal to all reg-}
isters during power-up. All internal registers will have their Q out-
V ^{U puts set low after a specified time (tpr, 1μs MAX). As a result, the}
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
E _IN ^{polarity of the output pins. This feature can greatly simplify state}
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
D _{T Input/Output Equivalent Schematics}
L ^{N PIN}
L _{O (VrefTypical = 3.2V)}
Vcc
Active Pull-up
Circuit
A _{C Vcc Vref Vcc}
ESD
Protection
IS ^Circuit
PIN
Feedback
Tri-State
Control
Active Pull-up
Circuit
(Vref Typical = 3.2V)
Vcc
Vref
D ^PIN
Data
Output
PIN
ESD
Protection
Circuit
Typical Input
Feedback
(To Input Buffer)
Typical Output
14