GAL18V10 Datasheet, PDF (14/16 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

Specifications GAL18V10
GAL18V10B: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2
1.1
PT H->L
PT L->H
1
0.9
0.8
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Normalized Tco vs Vcc
1.2
RISE
1.1
FALL
1
0.9
0.8
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Normalized Tsu vs Vcc
1.2
1.1
PT H->L
PT L->H
1
0.9
0.8
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Normalized Tpd vs Temp
1.3
1.2
PT H->L
PT L->H
1.1
1
0.9
0.8
0.7
-55
-25
0
25
50
75 100 125
Temperature (deg. C)
Normalized Tco vs Temp
1.3
1.2
RISE
FALL
1.1
1
0.9
0.8
0.7
-55
-25
0
25 50 75 100 125
Temperature (deg. C)
Normalized Tsu vs Temp
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
-55
PT H->L
PT L->H
-25
0
25
50
75 100 125
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
0
Delta Tco vs # of Outputs
Switching
0
-0.5
-0.5
-1
-1.5
-2
1
RISE
FALL
2 3 4 5 6 7 8 9 10
Number of Outputs Switching
-1
-1.5
-2
1
RISE
FALL
2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Delta Tpd vs Output Loading
10
8
RISE
6
FALL
4
2
0
-2
-4
0
50
100
150
200
250
300
Output Loading (pF)
Delta Tco vs Output Loading
10
8
RISE
6
FALL
4
2
0
-2
-4
0
50
100
150
200
250
300
Output Loading (pF)
14