ECP2 Datasheet, PDF (107/386 Pages) Lattice Semiconductor – LatticeECP2/M Family Data Sheet

Lattice Semiconductor
Pinout Information
LatticeECP2/M Family Data Sheet
LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.)
LFE2-6
LFE2-12
Pin Type
144
256
144
TQFP fpBGA TQFP
208
256
484
PQFP fpBGA fpBGA
Bank0
0
0
0
0
0
0
Bank1
0
0
0
0
0
0
Bank2
0
1
0
0
1
1
Bank3
Available DDR-Interfaces per I/O
Bank¹
Bank4
Bank5
0
0
0
0
0
0
0
2
0
0
2
3
0
1
0
0
1
3
Bank6
0
1
0
0
1
1
Bank7
0
1
0
0
1
1
Bank8
0
0
0
0
0
0
Bank0
0
0
0
0
0
0
Bank1
0
0
0
0
0
0
Bank2
0
0
0
0
0
0
Bank3
0
0
0
0
0
0
PCI Capable I/Os per Bank
Bank4
18
32
18
19
32
46
Bank5
8
14
10
18
17
46
Bank6
0
0
0
0
0
0
Bank7
0
0
0
0
0
0
Bank8
0
0
0
0
0
0
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
4-6