ISPPAC-POWR1014 Datasheet, PDF (10/45 Pages) Lattice Semiconductor – In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller

Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
I²C Port Characteristics¹
100KHz
400KHz
Symbol
Definition
Min. Max. Min. Max. Units
F_I2_C
I²C clock/data rate
100²
400² KHz
T_SU;STA
After start
4.7
0.6
us
T_HD;STA
After start
4
0.6
us
T_SU;DAT
Data setup
250
100
ns
T_SU;STO
Stop setup
4
0.6
us
T_HD;DAT
Data hold; SCL= Vih_min = 2.1V
0.3 3.45 0.3
0.9
us
T_LOW
Clock low period
4.7
10
1.3
10
us
T_HIGH
Clock high period
4
0.6
us
T_F
Fall time; 2.25V to 0.65V
300
300
ns
T_R
Rise time; 0.65V to 2.25V
1000
300
ns
T_TIMEOUT
Detect clock low timeout
25
35
25
35
ms
T_POR
Device must be operational after power-on reset
500
500
ms
T_BUF
Bus free time between stop and start condition
4.7
1.3
us
1. Applies to ispPAC-POWR1014A only.
2. If F_I2_C is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this
case, waiting for the T_CONVERT minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for
readout. When F_I2C is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.
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