PAC-POWR1208 Datasheet, PDF (1/6 Pages) Lattice Semiconductor – ispPAC-POWR1208 Evaluation Board

ispPAC-POWR1208 Evaluation Board
PAC-POWR1208-EV
April 2004
Application Note AN6040
Introduction
The Lattice Semiconductor ispPAC^®-POWR1208 In-System-Programmable Analog Circuit allows designers to
implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a
single integrated circuit. By integrating analog functions such as comparators and programmable slew rate FET
drivers with the digital functionality of a Programmable Logic Device (PLD), the ispPAC-POWR1208 provides the
power-supply designer with a rich set of features in a single device.
ISP™ (In-System-Programmability) provides the designer with an unprecedented level of flexibility, allowing him to
configure analog parameters such as threshold voltages as well as defining state machines and combinatorial logic
functions. All configuration data is stored internally in E²CMOS^® nonvolatile memory. Programming a configuration
is accomplished through an industry-standard JTAG IEEE 1149.1 interface.
PAC-POWR1208-EV Evaluation Board
The PAC-POWR1208-EV evaluation board (Figure 1) allows the designer to quickly configure and evaluate the isp-
PAC-POWR1208 on a fully assembled printed-circuit board. The double-sided board supports a 44-pin TQFP pack-
age, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user
prototyping. JTAG programming signals can be generated by using an ispDOWNLOAD^® programming cable con-
nected between the evaluation board and a PC’s parallel (printer) port. Both analog and digital features of the isp-
PAC-POWR1208 can be easily configured using PAC-Designer^® software.
Figure 1. PAC-POWR1208-EV Evaluation Board
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