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LC4032C Datasheet, PDF (1/74 Pages) Lattice Semiconductor – 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs | |||
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ispMACHTM 4000V/B/C/Z Family
July 2003
Features
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â High Performance
⢠fMAX = 400MHz maximum operating frequency
⢠tPD = 2.5ns propagation delay
⢠Up to four global clock pins with programmable
clock polarity control
⢠Up to 80 PTs per output
â Ease of Design
⢠Enhanced macrocells with individual clock,
reset, preset and clock enable controls
⢠Up to four global OE controls
⢠Individual local OE control per I/O pin
⢠Excellent First-Time-FitTM and reï¬t
⢠Fast path, SpeedLockingTM Path, and wide-PT
path
⢠Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
â Zero Power (ispMACH 4000Z) and Low
Power (ispMACH 4000V/B/C)
⢠Typical static current 10µA (4032Z)
⢠Typical static current 1.8mA (4000C)
⢠1.8V core low dynamic power
3.3V/2.5V/1.8V In-System Programmable
SuperFASTTM High Density PLDs
Data Sheet
â Broad Device Offering
⢠Multiple temperature range support
â Commercial: 0 to 90°C junction (Tj)
â Industrial: -40 to 105°C junction (Tj)
â Automotive: -40 to 130°C junction (Tj)
â Easy System Integration
⢠Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
⢠Operation with 3.3V (4000V), 2.5V (4000B) or
1.8V (4000C/Z) supplies
⢠5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
⢠Hot-socketing
⢠Open-drain capability
⢠Input pull-up, pull-down or bus-keeper
⢠Programmable output slew rate
⢠3.3V PCI compatible
⢠IEEE 1149.1 boundary scan testable
⢠3.3V/2.5V/1.8V In-System Programmable
(ISPâ¢) using IEEE 1532 compliant interface
⢠I/O pins with fast setup path
Table 1. ispMACH 4000V/B/C Family Selection Guide
Macrocells
User I/O Options
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltages (V)
Pins/Package
ispMACH
4032V/B/C
32
30/32
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
ispMACH
4064V/B/C
64
30/32/64
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
100 TQFP
ispMACH
4128V/B/C
128
64/92/96
2.7
1.8
2.7
333
3.3/2.5/1.8V
100 TQFP
128 TQFP
144 TQFP1
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O conï¬gurations.
ispMACH
4256V/B/C
256
64/96/128/160
3.0
2.0
2.7
322
3.3/2.5/1.8V
100 TQFP
144 TQFP1
176 TQFP
256 fpBGA2
ispMACH
4384V/B/C
384
128/192
3.5
2.0
2.7
322
3.3/2.5/1.8V
176 TQFP
256 fpBGA
ispMACH
4512V/B/C
512
128/208
3.5
2.0
2.7
322
3.3/2.5/1.8V
176 TQFP
256 fpBGA
Note: ispMACH 4032Z information is preliminary. ispMACH 4064Z/4128Z information is advance.
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speciï¬cations and information herein are subject to change without notice.
www.latticesemi.com
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