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LA-ISPMACH4000V Datasheet, PDF (1/42 Pages) Lattice Semiconductor – 3.3V/1.8V In-System Programmable SuperFAST High Density PLDs | |||
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LA-ispMACH 4000V/Z
Automotive Family
3.3V/1.8V In-System Programmable
SuperFAST TM High Density PLDs
July 2008
Data Sheet DS1017
Features
â High Performance
⢠fMAX = 168MHz maximum operating frequency
⢠tPD = 7.5ns propagation delay
⢠Up to four global clock pins with programmable
clock polarity control
⢠Up to 80 PTs per output
â Ease of Design
⢠Enhanced macrocells with individual clock,
reset, preset and clock enable controls
⢠Up to four global OE controls
⢠Individual local OE control per I/O pin
⢠Excellent First-Time-FitTM and reï¬t
⢠Fast path, SpeedLockingTM Path, and wide-PT
path
⢠Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
â Zero Power (LA-ispMACH 4000Z)
⢠Typical static current 10µA (4032Z)
⢠1.8V core low dynamic power
⢠LA-ispMACH 4000Z operational down to 1.6V
â AEC-Q100 Tested and Qualiï¬ed
⢠Automotive: -40 to 125°C ambient (TA)
â Easy System Integration
⢠Superior solution for power sensitive consumer
applications
⢠Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
⢠Operation with 3.3V (4000V) or 1.8V (4000Z)
supplies
⢠5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
⢠Hot-socketing
⢠Open-drain capability
⢠Input pull-up, pull-down or bus-keeper
⢠Programmable output slew rate
⢠3.3V PCI compatible
⢠IEEE 1149.1 boundary scan testable
⢠3.3V/2.5V/1.8V In-System Programmable
(ISPâ¢) using IEEE 1532 compliant interface
⢠I/O pins with fast setup path
⢠Lead-free (RoHS) package
Introduction
The high performance LA-ispMACH 4000V/Z automo-
tive family from Lattice offers a SuperFAST CPLD solu-
tion that is tested and qualiï¬ed to the AEC-Q100
standard. The family is a blend of Latticeâs two most
popular architectures: the ispLSI® 2000 and ispMACH
4A. Retaining the best of both families, the LA-ispMACH
4000V/Z architecture focuses on signiï¬cant innovations
to combine the highest performance with low power in a
ï¬exible CPLD family.
The LA-ispMACH 4000V/Z automotive family combines
high speed and low power with the ï¬exibility needed for
ease of design. With its robust Global Routing Pool and
Output Routing Pool, this family delivers excellent First-
Time-Fit, timing predictability, routing, pin-out retention
and density migration.
Table 1. LA-ispMACH 4000V Automotive Family Selection Guide
Macrocells
I/O + Dedicated Inputs
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltage (V)
Pins/Package
LA-ispMACH 4032V
32
30+2/32+4
7.5
4.5
4.5
168
3.3V
44-pin Lead-Free TQFP
48-pin Lead-Free TQFP
LA-ispMACH 4064V
64
30+2/32+4/64+10
7.5
4.5
4.5
168
3.3V
44-pin Lead-Free TQFP
48-pin Lead-Free TQFP
100-pin Lead-Free TQFP
LA-ispMACH 4128V
128
64+10/92+4/96+4
7.5
4.5
4.5
168
3.3V
100-pin Lead-Free TQFP
128-pin Lead-Free TQFP
144-pin Lead-Free TQFP
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speciï¬cations and information herein are subject to change without notice.
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