ISPLSI2064V Datasheet, PDF (1/14 Pages) Lattice Semiconductor – 3.3V High Density Programmable Logic

ispLSI^® 2064V
3.3V High Density Programmable Logic
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
Input Bus
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
Output Routing Pool (ORP)
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— The 64 I/O Pin Version is Fuse Map Compatible with
5V ispLSI 2064
• HIGH-PERFORMANCE E²CMOS^® TECHNOLOGY
— fmax = 100MHz Maximum Operating Frequency
A0
A1
A2
A3
GLB
B7
B6
B5
B4
S _{Global Routing Pool}
N _(GRP)
B3
IG ^{D Q}
B2
S ^{Logic D Q}
Array D Q
B1
E _{D Q}
D ^B0
— tpd = 7.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
W _{— Non-Volatile}
— 100% Tested at Time of Manufacture
E _{— Unused Product Term Shutdown Saves Power}
N _{• IN-SYSTEM PROGRAMMABLE}
— 3.3V In-System Programmability (ISP™) Using
R Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
O _{Capability, Allowing Easy Implementation of Wired-OR}
F ^{or Bus Arbitration Logic}
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
E _{— Reprogram Soldered Devices for Faster Prototyping}
V _{• THE EASE OF USE AND FAST SYSTEM SPEED OF}
4 PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
6 ^{— Enhanced Pin Locking Capability}
— Three Dedicated Clock Input Pins
0 _{— Synchronous and Asynchronous Clocks}
2 _{— Programmable Output Slew Rate Control}
I — Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
S _{Interconnectivity}
L _{• ispDesignEXPERT™ – LOGIC COMPILER AND COM-}
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
p _{SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING}
is ^{— Superior Quality of Results}
A4
A5
A6
A7
Output Routing Pool (ORP)
Input Bus
Description
0139A/2064V
The ispLSI 2064V is a High Density Programmable Logic
Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064V features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP). The ispLSI 2064V offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064V device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
E _{Tools, Timing Simulator and ispANALYZER™}
US ^{— PC and UNIX Platforms}
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
September 2000
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