ISPLSI2032A Datasheet, PDF (1/15 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

ispLSI^® 2032/A
In-System Programmable High Density PLD
Features
Functional Block Diagram
• ENHANCEMENTS
— ispLSI 2032A is Fully Form and Function Compatible
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging
— ispLSI 2032A is Built on an Advanced 0.35 Micron
E²CMOS^® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
A0
A1
A2 GLB
NS Global Routing Pool
(GRP)
A7
IG _{D Q}
A6
S _{D Q}
Logic
E Array D Q
A5
D^{D Q}
• HIGH PERFORMANCE E²CMOS^® TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
NEW ^A3
A4
0139Bisp/2000
— Non-Volatile
— 100% Tested at Time of Manufacture
R _{— Unused Product Term Shutdown Saves Power}
O • IN-SYSTEM PROGRAMMABLE
F ^{— In-System Programmable (ISP™) 5V Only}
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
E _{— Reprogram Soldered Devices for Faster Prototyping}
2 _{• OFFERS THE EASE OF USE AND FAST SYSTEM}
3 _{SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY}
0 OF FIELD PROGRAMMABLE GATE ARRAYS
2 — Complete Programmable Device Can Combine Glue
Logic and Structured Designs
I _{— Enhanced Pin Locking Capability}
S _{— Three Dedicated Clock Input Pins}
L ^{— Synchronous and Asynchronous Clocks}
— Programmable Output Slew Rate Control to
p _{Minimize Switching Noise}
is ^{— Flexible Pin Placement}
Description
The ispLSI 2032 and 2032A are High Density Program-
mable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2032 and 2032A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2032 and 2032A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
(Figure 1). There are a total of eight GLBs in the ispLSI
2032 and 2032A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
— Optimized Global Routing Pool Provides Global
USE ^{Interconnectivity}
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
January 2002
2032_10
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