ISPLSI1048E_06 Datasheet, PDF (1/17 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

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ispLSI^® 1048E
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
Output Routing Pool
Output Routing Pool
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pin-out Compatible to ispLSI 1048C
• HIGH PERFORMANCE E²CMOS^® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
F7 F6 F5 F4 F3 F2 F1 F0
E7 E6 E5 E4 E3 E2 E1 E0
A0
D7
A1
DQ
D6
S _A2
D5
DQ
A3
Logic
D4
N _{Global Routing Pool (GRP)}
A4
Array D Q ^GLB
D3
A5
D2
IG ^{D Q}
A6
D1
A7
D0
S _{B0 B1 B2 B3 B4 B5 B6 B7}
DE ^{Output Routing Pool}
C0 C1 C2 C3 C4 C5 C6 C7
CLK
Output Routing Pool
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
W _{— Electrically Eraseable and Reprogrammable}
E _{— Non-Volatile}
N ^{— 100% Tested at Time of Manufacture}
• IN-SYSTEM PROGRAMMABLE
R _{— In-System Programmable (ISP™) 5V Only}
— Increased Manufacturing Yields, Reduced Time-to-
O _{Market and Improved Product Quality}
F _{— Reprogram Soldered Devices for Faster Prototyping}
A ^{• OFFERS THE EASE OF USE AND FAST SYSTEM}
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
E _{OF FIELD PROGRAMMABLE GATE ARRAYS}
8 — Complete Programmable Device Can Combine Glue
4 ^{Logic and Structured Designs}
0 ^{— Enhanced Pin Locking Capability}
1 ^{— Four Dedicated Clock Input Pins}
I ^{— Synchronous and Asynchronous Clocks}
— Programmable Output Slew Rate Control to
S _{Minimize Switching Noise}
L _{— Flexible Pin Placement}
p _{— Optimized Global Routing Pool Provides Global}
is ^{Interconnectivity}
0139G1A-isp
Description
The ispLSI 1048E is a High Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1048 archi-
tecture, the ispLSI 1048E device adds two new global
output enable pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
USE ^{— Lead-Free Package Options}
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
August 2006
1048e_12
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