ISPLSI1032 Datasheet, PDF (1/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

ispLSI^® 1032
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
Output Routing Pool
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
D7 D6 D5 D4 D3 D2 D1 D0
— Wide Input Gating for Fast Counters, State
A0
C7
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
A1
DQ
C6
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E²CMOS^® TECHNOLOGY
W _{— fmax = 90 MHz Maximum Operating Frequency}
E ^L _{— fmax = 60 MHz for Industrial and Military/883 Devices}
N _IA ^{— tpd = 12 ns Propagation Delay}
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
R ^R — Non-Volatile E²CMOS Technology
O ^{T — 100% Tested}
• IN-SYSTEM PROGRAMMABLE
F ^S — In-System Programmable™ (ISP™) 5-Volt Only
U ^{— Increased Manufacturing Yields, Reduced Time-to-}
Market, and Improved Product Quality
2E ^{D — Reprogram Soldered Devices for Faster Prototyping}
• COMBINES EASE OF USE AND THE FAST SYSTEM
3 _{IN SPEED OF PLDs WITH THE DENSITY AND FLEX-}
0 ^{IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS}
1 ^{S — Complete Programmable Device Can Combine Glue}
& _{Logic and Structured Designs}
I ^N _{— Four Dedicated Clock Input Pins}
LS _IAL ^{IG — Synchronous and Asynchronous Clocks}
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
p ^{S Interconnectivity}
is ^{C E • ispDesignEXPERT™ – LOGIC COMPILER AND COM-}
R ^{PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL}
D _{SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING}
E ^{E — Superior Quality of Results}
— Tightly Integrated with Leading CAE Vendor Tools
S M — Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
U _{COM — PC and UNIX Platforms}
A2
DQ
C5
Logic
A3
Array D Q ^GLB
C4
A4
C3
DQ
A5
C2
A6
C1
A7 ^{Global Routing Pool (GRP)} C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
Description
The ispLSI 1032 is a High-Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1032 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1032 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
March 1999
1032_07
1