ISPGAL22V10 Datasheet, PDF (1/15 Pages) Lattice Semiconductor – In-System Programmable E2CMOS PLD

Specificat_iio_sn_ps _Gisp_AG_LA₂L₂22_VV₁1₀0
In-System Programmable E²CMOS PLD
Generic Array Logic™
FEATURES
• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
• HIGH PERFORMANCE E²CMOS^® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5 ns Maximum from Clock Input to Data Output
— UltraMOS^® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
• E² CELL TECHNOLOGY
— In-System Programmable Logic
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E²) floating gate technology to provide the industry's
first in-system programmable 22V10 device. E² technology of-
fers high speed (<100ms) erase times, providing the ability to re-
program or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The ispGAL22V10 is fully function/fuse map/parametric
compatible with standard bipolar and CMOS 22V10 devices. The
standard PLCC package provides the same functional pinout as
the standard 22V10 PLCC package with No-Connect pins being
used for the ISP interface signals.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 10,000 erase/write
cycles and data retention in excess of 20 years are specified.
FUNCTIONAL BLOCK DIAGRAM
I/CLK
I
I
I
I
I
I
I
I
I
I
SDO
SDI
MODE
SCLK
I
PROGRAMMING
LOGIC
PIN CONFIGURATION
RESET
8
OLMC
10
OLMC
12
OLMC
14
OLMC
16
OLMC
16
OLMC
14
OLMC
12
OLMC
10
OLMC
8
OLMC
PRESET
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
PLCC
SSOP
4
2
28
26
I5
2 5 I/O/Q
SCLK
I/CLK
1
28 Vcc
I/O/Q
I
I7
MODE
I9
ispGAL22V10
Top View
I/O/Q
I
I/O/Q
I
I/O/Q
2 3 I/O/Q
I
ispGAL ^I/O/Q
SDO
22V10 ^I
I7
I/O/Q
22 SDO
MODE
I/O/Q
2 1 I/O/Q
I Top View I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I 11 ₁₂
14
16
1 8 ^{1 9 I/O/Q}
I
GND 14
I
15 SDI
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-888-ISP-PLDS; FAX [phone]; http://www.latticesemi.com
July 1997
isp22v10_02
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