ISPCLOCK5600A Datasheet, PDF (1/51 Pages) Lattice Semiconductor – In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer

ispClock^™5600A Family
In-System Programmable, Enhanced Zero-Delay
Clock Generator with Universal Fan-Out Buffer
June 2008
Data Sheet DS1019
Features
■ 8MHz to 400MHz Input/Output Operation
■ Low Output to Output Skew (<50ps)
■ Low Jitter Peak-to-Peak
■ Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL,
LVDS, LVPECL, Differential HSTL, SSTL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual V_CCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■ Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (1 to 40)
- Feedback divider (1 to 40)
- Five output dividers (2 to 80)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
■ Precision Programmable Phase Adjustment
(Skew) Per Output
• 16 settings; minimum step size 156ps
- Locked to VCO frequency
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
■ Up to Five Clock Frequency Domains
■ Flexible Clock Reference and External
Feedback Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, SSTL
• Clock A/B selection multiplexer
• Feedback A/B selection multiplexer
• Programmable termination
■ All Inputs and Outputs are Hot Socket
Compliant
■ Four User-programmable Profiles Stored in
E²CMOS^® Memory
• Supports both test and multiple operating
configurations
■ Full JTAG Boundary Scan Test In-System
Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■ 100-pin and 48-pin TQFP Packages
■ Applications
• Circuit board common clock generation and
distribution
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer
Product Family Block Diagram
LOCK DETECT
M
*
PHASE/
FREQUENCY
FILTER
DETECTOR
N
PLL CORE
Internal/External
Feedback
Select
JTAG
INTERFACE
&
E²CMOS
*
MEMORY
* Input Available only on ispClock5620A
BYPASS
MUX
VCO
OUTPUT
DIVIDERS
V0
V1
V2
V3
V4
Multiple Profile
Management Logic
0123
INTERNAL FEEDBACK PATH
SKEW
OUTPUT
CONTROL DRIVERS
OUTPUT
ROUTING
MATRIX
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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