ISPCLOCK5500 Datasheet, PDF (1/48 Pages) Lattice Semiconductor – In-System Programmable Clock Generator with Universal Fan-Out Buffer


ispClock^™5500 Family
In-System Programmable Clock Generator
with Universal Fan-Out Buffer
March 2005
Data Sheet
Features
■ 10MHz to 320MHz Input/Output Operation
■ Low Output to Output Skew (<50ps)
■ Low Jitter Peak-to-Peak(<70ps)
■ Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,
LVPECL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual V_CCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■ Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (5 bits)
- Internal feedback divider (5 bits)
- Five output dividers (5 bits)
• Programmable On-chip Loop Filter
■ Precision Programmable Phase Adjustment
(Skew) Per Output
• 16 settings; minimum step size 195ps
- Locked to VCO frequency
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
Product Family Block Diagram
■ Up to Five Clock Frequency Domains
■ Flexible Clock Reference Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL
• Clock A/B selection multiplexer
• Programmable precision termination
■ Four User-programmable Profiles Stored in
E²CMOS^® Memory
• Supports both test and multiple operating
configurations
■ Full JTAG Boundary Scan Test In-System
Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■ 100-pin and 48-pin TQFP Packages
■ Applications
• Circuit board common clock generation and
distribution
• PLL-based frequency generation
• High fan-out clock buffer
LOCK DETECT
M
*
PHASE/
FREQUENCY
FILTER
DETECTOR
N
PLL CORE
JTAG
INTERFACE
&
E²CMOS
MEMORY
* Input Available only on ispClock 5520
BYPASS
MUX
VCO
OUTPUT
DIVIDERS
V0
V1
V2
V3
V4
Multiple Profile
Management Logic
0123
INTERNAL FEEDBACK PATH
SKEW
OUTPUT
CONTROL DRIVERS
OUTPUT
ROUTING
MATRIX
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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