GAL22LV10 Datasheet, PDF (1/18 Pages) Lattice Semiconductor – Low Voltage E2CMOS PLD Generic Array Logic™

FEATURES
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• HIGH PERFORMANCE E²CMOS^® TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3 ns Maximum from Clock Input to Data Output
— UltraMOS^® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices
(GAL22LV10C)
• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
• E² CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
The GAL22LV10D, at 4 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL22LV10C can interface with both 3.3V and 5V
signal levels. The GAL22LV10 is manufactured using Lattice
Semiconductor's advanced 3.3V E²CMOS process, which com-
bines CMOS with Electrically Erasable (E²) floating gate technol-
ogy. High speed erase times (<100ms) allow the devices to be
reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are specified.
GAL22LV10
Low Voltage E²CMOS PLD
Generic Array Logic™
FUNCTIONAL BLOCK DIAGRAM
I/CLK
I
I
I
I
RESET
8
OLMC
10
OLMC
12
OLMC
14
OLMC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
16
I
OLMC
I/O/Q
16
I
OLMC
I/O/Q
I
14
OLMC
I/O/Q
I
12
OLMC
I
10
OLMC
I
8
OLMC
I
PIN CONFIGURATION
PRESET
PLCC
I/O/Q
I/O/Q
I/O/Q
4
I5
I
I7
NC
I9
I
I 11
12
2
28
26
25 I/O/Q
GAL22LV10
Top View
I/O/Q
23 I/O/Q
NC
21 I/O/Q
I/O/Q
19 I/O/Q
14
16
18
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-888-ISP-PLDS; FAX [phone]; http://www.latticesemi.com
July 1997
22lv10_03
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