GAL20XV10 Datasheet, PDF (1/14 Pages) Lattice Semiconductor – High-Speed E2CMOS PLD Generic Array Logic

GAL20XV10
High-Speed E²CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E²CMOS ^® TECHNOLOGY
— 10 ns Maximum Propagation Delay
I/CLK
— Fmax = 100 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS^® Advanced CMOS Technology
I
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 90mA Maximum Icc
I
— 75mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
I
4
OLMC
4
OLMC
4
OLMC
I/O/Q
I/O/Q
I/O/Q
• E² CELL TECHNOLOGY
— Reconfigurable Logic
I
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
I
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
I
— XOR Gate Capability on all Outputs
— Full Function and Parametric Compatibility with
PAL12L10, 20L10, 20X10, 20X8, 20X4
I
— Registered or Combinatorial with Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
I
• APPLICATIONS INCLUDE:
— High Speed Counters
I
— Graphics Processing
— Comparators
I
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Description
I/OE
The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E²) floating gate technology to provide
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counter-
parts. E²CMOS technology offers high speed (<100ms) erase
times providing the ability to reprogram, reconfigure or test the de-
vices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL20XV10 are the PAL^® architectures
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4
I5
2
28
26
25 I/O/Q
I
I/O/Q
I 7 _GAL20XV10 23 I/O/Q
NC
NC
I 9 Top View 21 I/O/Q
I
I/O/Q
I 11
19 I/O/Q
12
14
16
18
DIP
I/CLK ¹
I
24 Vcc
I/O/Q
I
I/O/Q
I
GAL
I/O/Q
20XV10
I
I/O/Q
I6
I/O/Q
I
18 I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
GND 12
13 I/OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-888-ISP-PLDS; FAX [phone]; http://www.latticesemi.com
July 1997
20xv10_02
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