GAL20VP8 Datasheet, PDF (1/17 Pages) Lattice Semiconductor – High-Speed E2CMOS PLD Generic Array Logic

GAL20VP8
High-Speed E²CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• HIGH DRIVE E²CMOS^® GAL^® DEVICE
— TTL Compatible 64 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 80 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS^® Advanced CMOS Technology
• ENHANCED INPUT AND OUTPUT FEATURES
— Schmitt Trigger Inputs
— Programmable Open-Drain or Totem-Pole Outputs
— Active Pull-Ups on All Inputs and I/O pins
• E² CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Compatible with Standard GAL20V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Ideal for Bus Control & Bus Arbitration Logic
— Bus Address Decode Logic
— Memory Address, Data and Control Circuits
— DMA Control
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I/CLK
I
I
I
I
I
I
I
I
I
IMUX
CLK
8 OLMC
8 _OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
OE
IMUX
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
Description
The GAL20VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations. The GAL20VP8 is manufactured using Lattice
Semiconductor's advanced E²CMOS process which combines
CMOS with Electrically Erasable (E²) floating gate technology. High
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently.
System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL20VP8
combines the familiar GAL20V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex-
ibility by allowing the Output Logic Macrocell (OLMC) to be con-
figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus-driving capability.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4
I5
2
28
26
25 I/O/Q
I
I/O/Q
Vcc 7 _GAL20VP8 23 I/O/Q
NC
NC
I9
Top View ^{21 GND}
I
I/O/Q
I 11
19 I/O/Q
12
14
16
18
DIP
I/CLK ¹
I
24 I
I
I
I/O/Q
I
GAL
I/O/Q
I 20VP8 I/O/Q
Vcc 6
I/O/Q
I
18 GND
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I/OE ¹²
13 I
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
December 1997
20vp8_03
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