GAL20V8Z Datasheet, PDF (1/19 Pages) Lattice Semiconductor – Zero Power E2CMOS PLD

Features
• ZERO POWER E²CMOS TECHNOLOGY
— 100µA Standby Current
— Input Transition Detection on GAL20V8Z
— Dedicated Power-down Pin on GAL20V8ZD
— Input and Output Latching During Power Down
• HIGH PERFORMANCE E²CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS^® Advanced CMOS Technology
• E² CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL20V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL20V8Z
GAL20V8ZD
Zero Power E²CMOS PLD
Functional Block Diagram
I/CLK
I
I
I/DPP
IMUX
CLK
8 OLMC
8 OLMC
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
I
8 OLMC
OE
I
IMUX
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
Description
The GAL20V8Z and GAL20V8ZD, at 100 µA standby current and
12ns propagation delay provides the highest speed and lowest
power combination PLD available in the market. The
GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad-
vanced zero power E²CMOS process, which combines CMOS with
Electrically Erasable (E²) floating gate technology.
The GAL20V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full func-
tionality of the standard GAL20V8. The GAL20V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 19 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
DIP
PLCC
I/CLK
I
I
4
2
28
26
I/DPP 5
2 5 I/O/Q ^{I/D P P}
I
GAL20V8Z
I/O/Q
I
I7
2 3 I/O/Q
I
GAL20V8ZD
NC
NC
I
I9
Top View
2 1 I/O/Q
I
I
I/O/Q
I
I 11 ₁₂
14
16
1 8 ^{1 9 I/O/Q}
I
I
GND
1
24 Vcc
2
23 I
3 _GAL 22
4 _20V8Z 21
5 _20V8ZD 20
6
19
I/O/Q
I/O/Q
I/O/Q
I/O/Q
7
18 I/O/Q
8
17 I/O/Q
9
16 I/O/Q
10
15 I/O/Q
11
14 I
12
13 I/OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
December 1997
20v8zzd_03
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