GAL16V811111 Datasheet, PDF (1/23 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

FEATURES
• HIGH PERFORMANCE E²CMOS^® TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS^® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E² CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL^® Devices with Full Func-
tion/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Specificatio_Gns_AG_LA₁L1₆6_VV₈8
High Performance E²CMOS PLD
Generic Array Logic™
FUNCTIONAL BLOCK DIAGRAM
I/CLK
CLK
8 _OLMC
I/O/Q
I
8 OLMC
I/O/Q
I
8 OLMC
I/O/Q
I
8 OLMC
I/O/Q
I
8 OLMC
I/O/Q
I
8 OLMC
I/O/Q
I
8 ^OLMC
I/O/Q
I
8 ^OLMC
I/O/Q
I
OE
I/OE
DESCRIPTION
The GAL16V8C, at 5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E²) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL16V8 are the PAL architectures
listed in the table of the macrocell description section. GAL16V8
devices are capable of emulating any of these PAL architectures
with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor guarantees 100% field programmability
and functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are guaranteed.
PIN CONFIGURATION
PLCC
I
I4
I I/CLK Vcc I/O/Q
2
20
18
I/O/Q
I
GAL16V8
I/O/Q
I6
16 I/O/Q
Top View
I
I/O/Q
I8
14 I/O/Q
9
11
13
I GND I/OE I/O/Q I/O/Q
DIP
I/CLK
I
I
I
I
I
I
I
I
GND
1
20 Vcc
I/O/Q
GAL
16V8
5
I/O/Q
I/O/Q
I/O/Q
15 I/O/Q
I/O/Q
I/O/Q
I/O/Q
10
11 I/OE
Copyright © 1996 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, L with Lattice Semiconductor Corp. and L (Stylized) are registered
trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD,
ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice
Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-888-ISP-PLDS; FAX [phone]; http://www₃.l_-a₆tt₅ice.com
1996 Data Book
1996 Data Book