GAL16LV8ZD Datasheet, PDF (1/18 Pages) Lattice Semiconductor – Low Voltage, Zero Power E2CMOS PLD Generic Array Logic

Features
• 3.3V LOW VOLTAGE, ZERO POWER OPERATION
— JEDEC Compatible 3.3V Interface Standard
— Interfaces with Standard 5V TTL Devices
— 50µA Typical Standby Current (100µA Max.)
— 45mA Typical Active Current (55mA Max.)
— Dedicated Power-down Pin
• HIGH PERFORMANCE E²CMOS TECHNOLOGY
— TTL Compatible Balanced 8 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 62.5 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS^® Advanced CMOS Technology
• E² CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— Ideal for Mixed 3.3V and 5V Systems
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL16LV8ZD
Low Voltage, Zero Power E²CMOS PLD
Generic Array Logic™
Functional Block Diagram
I/CLK
CLK
I
I
DPP
I
I
I
I
I
8 _OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 ^OLMC
8 ^OLMC
OE
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
Description
The GAL16LV8ZD, at 100 µA standby current and 15ns propagation
delay provides the highest speed low-voltage PLD available in the
market. The GAL16LV8ZD is manufactured using Lattice
Semiconductor's advanced 3.3V E²CMOS process, which com-
bines CMOS with Electrically Erasable (E²) floating gate technology.
The GAL16LV8ZD utilizes a dedicated power-down pin (DPP) to
put the device into standby mode. It has 15 inputs available to the
AND array and is capable of interfacing with both 3.3V and stan-
dard 5V devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I
DPP 4
I I/CLK Vcc I/O/Q
2
20
18
I/O/Q
I
I6
I
GAL16LV8ZD
Top View
I/O/Q
16 I/O/Q
I/O/Q
I8
9
14 I/O/Q
11
13
I GND I/OE I/O/Q I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
December 1997
16lv8zd_03
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