3256A Datasheet, PDF (1/13 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

ispLSI ^® 3256A
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 128 I/O Pins
— 11000 PLD Gates
— 384 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E²CMOS^® TECHNOLOGY
— fmax = 90 MHz Maximum Operating Frequency
— tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP™) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
mize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
H3 H2 H1 H0
Output Routing Pool
G3 G2 G1 G0
Boundary
Scan
A0
DQ
F3
A1
DQ
OR
F2
A2
Array D Q
F1
DQ
A3
Twin
F0
DQ
GLB
DQ
OR
B0
Array D Q
E3
B1
DQ
E2
B2
E1
Global Routing Pool
B3
E0
C0 C1 C2 C3
Output Routing Pool
D0 D1 D2 D3
Output Routing Pool
0139A
Description
The ispLSI 3256A is a High-Density Programmable Logic
Device containing 384 Registers, 128 Universal I/O pins,
five Dedicated Clock Input Pins, eight Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3256A features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256A offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3256A device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256A
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays, and eight
outputs which can be configured to be either combinato-
rial or registered. All Twin GLB inputs come from the
GRP.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
May 1999
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