ML620Q131B Datasheet, PDF (5/34 Pages) LAPIS Semiconductor Co., Ltd. – 16-bit micro controller

BLOCK DIAGRAM
ML620Q131B/ML620Q132B/ML620Q133B Block Diagram
“*” indicates the secondary, tertiary or quarternary function.
FEDL620Q130B-01
ML620Q131B/2B/3B/4B/5B/6B
VDD
VSS
VDDL
RESET N
TEST0
TEST1_N
OSC0*
OSC1*
LSCLK*
OUTCLK*
AIN0 to AIN5*
CMP0P*
CMP0M*
CMP1P*
EPSW1～3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U16/100)
GREG
0～15
ELR1～3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
Power
RAM
2Kbyte
RESET &
TEST
INT
OSC
1
INT
1
SA-ADC
INT
Analog
2
Comparator
×2
Interrupt
Controller
INT
1
WDT
INT
3
TBC
INT
2
VLS
INT
1
DME
ECSR1～3
DSR/CSR
PC
BUS
Controller
Program
Memory
(FLASH)
8/16/24Kbyte
INT
SSIOx1
1
INT
2
UART
INT
2
I2C
Master/Slave
INT
10
8bit Timer
×10
INT
1
PWM
SCK0*
SIN0*
SOUT0*
RXD0*
TXD0*
RXD1*
TXD1*
SDA0*
SCL0*
PWMC*
INT
5
GPIO
PA0 to PA2
PB0 to PB7
Figure 1-1 ML620Q131B/ML620Q132B/ML620Q133B Block Diagram
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