MR45V256A Datasheet, PDF (4/21 Pages) List of Unclassifed Manufacturers – 256k(32,768-Word  8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI

SPI mode0（CPOL=0, CPHA=0）
CS#
SCK
SI
MSB
FEDR45V256A-01
MR45V256A
LSB
SPI mode3（CPOL=1, CPHA=1）
CS#
SCK
SI
MSB
LSB
Status Register
b7
SRWD
0
0
0
Status Register Write Disable
b0
BP1 BP0 WEL WIP
Block Protect Bits
Write Enable Latch
Write In Progress (Always 0)
Name
WIP
WEL
BP0,BP1
SRWD
0
Function
Fixed to 0.
Write Enable Latch. This indicates internal WEL condition.
Block Protect :These bits can be changed protect area .
This is the software protect.
Status Register Write Disable （ SRWD ） : SRWD controls the effect of the
hardware WP# pin. This device will be in hardware-protect by combination of
SRWD and WP#.
Fixed to 0.
Status Register data are volatile.
Set Status Register data by WRSR(Write status register) command, after power on.
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