ML7074-004 Datasheet, PDF (33/98 Pages) OKI electronic componets – VoIP CODEC

FEDL7074-003-01
ML7074-004
Method of Accessing Transmit and Receive Buffers
A. In the Frame Mode (CR11-B7 = “0”)
The control timing and the method of accessing the transmit buffer (TX Buffer) during the frame mode are shown
in Fig. 20. When the transmit buffer, which stores the compressed speech data of the transmit side (the speech
compressing side), becomes full, a read request is made to the MPU by taking FR0B from the “H” state to the “L”
state. Read the data in the transmit buffer during the following timing. The read address of the transmit buffer
during the following timing. The read address of the transmit buffer is “10xxxxxxb” in which the lower 6 bits are
ignored. Further, FR0B will be maintained in the “L” state until all the data bytes in the transmit buffer are read
out.
FR0B
A7-A0
D15-D0
CSB
WRB
RDB
Address
Data 0
Address
Data n-1
(Transmit buffer full)
Address = 10xxxxxxb (fixed)
Number of data = n words
(Transmit buffer empty)
Fig. 20 Transmit buffer control timing
The control timing of the receive buffer (RX buffer) in the frame mode is shown in Fig. 21. A write request is made
to the MPU by taking FR1B from the “H” state to the “L” state indicating that the receive buffer for storing the
speech compression data of the receive side (the speech decompression side) has become empty. Write data into
the receive buffer at the following timing. The write address of the receive buffer is “01xxxxxxb” in which the
lower 6 bits are ignored. Further, FR1B will be maintained in the “L” state until the receive buffer is written to
become full.
FR1B
A7-A0
D15-D0
CSB
WRB
RDB
Address
Data 0
Address
Data n-1
(Receive buffer empty)
Address = 01xxxxxxb (fixed)
Number of data = n words
(Receive buffer full)
Fig. 21 Receive buffer control timing
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