MR45V032A Datasheet, PDF (3/21 Pages) List of Unclassifed Manufacturers – 32k (4,096-Word x 8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI

FEDR45V032A-01
MR45V032A
PIN DESCRIPTIONS
Pin Name
Description
Chip Select (input, negative logic)
CS#
Latches an address by low input, activates the FeRAM, and enables a read or write
operation.
WP#
Write Protect( input , negative logic )
Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should
be fixed low or high in write-operations.
HOLD( input , negative logic )
HOLD#
Hold pin is used when the serial-communication suspended without disable the chip
select. When HOLD# is low ,the serial-output is in High-Z status and
serial-input/serial-clock are “Don’t Care” . CS# should be low in hold operation.
SCK
Serial Clock
Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on
the rising edge and output occur on the falling edge.
Serial input
SI
SI pins are serial input pins for Operation-code , addresses ,and data-inputs .
Serial output
SO
SO pins are serial output pins.
V_CC, V_SS
Power supply
Apply the specified voltage to V_CC. Connect V_SS to ground.
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