MR27V6441L Datasheet, PDF (11/15 Pages) LAPIS Semiconductor Co., Ltd. – 64M–Word × 1–Bit Serial Production Programmed ROM (P2ROM)

FEDR27V6441L-002-03
MR27V6441L / P2ROM
Fast Read Array Timing Waveform
#CS
SCLK
SI
SO
*note1
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3
1^st byte Command
2^nd byte AD1
Hi-Z
#CS
SCLK
SI
SO
*note2
BIT 1 BIT 0
Don’t Care
5^th byte DUMMY
Hi-Z
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5
1^st data output
2^nd data output
#CS
SCLK
SI
SO
BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7
Hi-Z
(N-1)^th data output
N^th data output
(N+1)^th data output
Note:
1. Input data are latched at SCLK-rising edge.
2. Data-output starts at SCLK-falling edge in bit0 of the 5^th byte.
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