KKF8574 Datasheet, PDF (3/11 Pages) KODENSHI KOREA CORP. – silicon CMOS circuit.

KKF8574
System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
System configuration.
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH
level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse,
set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to
enable the master to generate a stop condition.
Acknowledgement on the I²C-bus.
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