KK82C55 Datasheet, PDF (1/22 Pages) KODENSHI KOREA CORP. – CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

TECHNICAL DATA
KK82C55
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
The Integral KK82C55AN is a high-performance, CHMOS version of the industry standard
KK82C55AN general purpose programmable I/O device which is designed for use with all Intel and
most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2
groups of 12 and used in 3 major modes of operation.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or
outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the
remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-
directional bus configuration.
FEATURES
• Compatible with all Intel and Most Other Microprocessors
• High Speed, «Zero Wait State» Operation with 8MHz 8086/88 and 80186/188
• 24 Programmable I/O Pins
• Low Power CHMOS
• Completely TTL Compatible
• Control Word Read-Back Capability
• Direct Bit Set/Reset Capability
• 2.5mA DC Drive Capability on all I/O Port Outputs
• Available in 40-Pin DIP
• Available in EXPRESS
ƒ Standard Temperature Range
ƒ Extended Temperature Range
ƒ
GROUP
A
CONTROL
D7-D0
DATA
BUS
BUFFER
8 BIT
INTERNAL
DATA BUS
RD
WR
A1
A0
Reset
CS
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
Figure 1
GROUP
A
PORT
A
(8)
GROUP
A
PORT C
UPPER
(4)
GROUP
B
PORT C
LOWER
(4)
GROUP
B
PORT
B
(8)
PA7-PA0
PC7-PC4
PC3-PC0
PB7-PB0
PA₃
PA₂
PA₁
PA₀
RD
CS
V_SS
A₁
A₀
PC₇
PC₆
PC₅
PC₄
PC₀
PC₁
PC₂
PC₃
PB₀
PB₁
PB₂
1.
40
2.
39
3.
38
4.
37
5.
36
6.
35
7.
34
8.
33
9.
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
Figure 2
PA₄
PA₅
PA₆
PA₇
WR
Reset
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
V_CC
PB₇
PB₆
PB₅
PB₄
PB₃
1