KK74LV273 Datasheet, PDF (1/7 Pages) KODENSHI KOREA CORP. – Octal D Flip-Flop with Common Clock and Reset

TECHNICAL DATA
Octal D Flip-Flop with Common Clock and Reset
KK74LV273
The KK74LV273 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT273.
The KK74LV273 has eight edge-triggered, D-type flip-flops with individual
D inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip-flops simultaneously. The state of each
D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop. All outputs
will be forced LOW independently of clock or data inputs by a LOW
voltage level on the MR input. The device is useful for applications where
the true output only is required and the clock and master reset are common
to all storage elements.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC_S
• Supply voltage range: 1.2 to 5.5 V
• Low input current: 1.0 µА; 0.1 µА at Т = 25 °С
• High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
KK74LV273N
Plastic DIP
KK74LV273DW
SOIC
T_A = -40° to 125° C for all packages
LOGIC DIAGRAM
PIN 20=V_CC
PIN 10 = GND
PIN ASSIGNMENT
RESET 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 V _CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CLOCK
FUNCTION TABLE
Inputs
Reset Clock
D
L
X
X
H
H
H
L
H
L
X
H
X
H= high level
L = low level
X = don’t care
Z = high impedance
Output
Q
L
H
L
no change
no change
1