KK74LV174 Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Hex D-type flip-flop with reset; positive edge-trigger

TECHNICAL DATA
Hex D-type flip-flop with reset; positive edge-trigger
KK74LV174
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with individual D
inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip–flops simultaneously.
The register is fully edge–triggered. The state of each D input, one set–up
time prior to the LOW–to–HIGH clock transition, is transferred to the
corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently of
clock or data inputs.
The device is useful for applications requiring true outputs only and clock
and master reset inputs that are common to all storage elements.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC_S
• Supply voltage range: 1.2 to 5.5 V
• Low input current: 1.0 µА; 0.1 µА at Т = 25 °С
• Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V
• High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
KK74LV174N Plastic
KK74LV174D SOIC
T_A = -40° to 125° C for all packages
PIN ASSIGNMENT
MR ₁
Q0 ₂
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND 8
16 V _CC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP
CP
MR
PIN 16=V_CC
PIN 08 = GND
FUNCTION TABLE
Inputs
MR
CP
L
X
H
H
H
L
H
H= high level
L = low level
X = don’t care
Outputs
Dn
Qn
X
L
H
H
L
L
X no change
X no change
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