KK74LV164 Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER

TECHNICAL DATA
KK74LV164
8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
The KK74LV164 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the KK74HC/HCT164.
The KK74LV164 is an 8-bit edge-triggered shift register with serial
data entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (DSA or DSB); either input can be used
as an active HIGH enable for data entry through the other input. Both
inputs must be connected together or an unused input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of
the clock (CP) input and enters into Q₀, which is the logical AND of the
two data inputs (DSA, DSB ) that existed one set-up time prior to the rising
clock edge.
A LOW on the master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all outputs LOW.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 1.2 to 5.5 V
• Low Input Current: 1.0 µA, 0.1 µА at Т = 25 °С
• Output Current: 6 mA at V_CC = 3.0 V; 12 mA at V_CC = 4.5 V
• High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
14
1
14
1
D SUFFIX
SO
ORDERING INFORMATION
KK74LV164N
KK74LV164D
Plastic
SOIC
T_A = -40° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
SERIAL
1
DSA
DATA
2
INPUTS DSB
DATA
8
CP
2 _Q0
4 _Q1
5 _Q2
6 _Q3
10 _Q4
11 _Q5
12 _Q6
13 _Q7
PARALLEL
DATA
OUTPUTS
DSA 1
DSB 2
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
14 V_CC
13 Q7
12 Q6
11 Q5
10 Q4
9 MR
8 CP
FUNCTION TABLE
Inputs
Outputs
9
MR
MR CP DSA DSB Q0 Q1 ... Q7
L
X X X L L…L
PIN 14=V_CC
PIN 7 = GND
H
L L L Q0 ... Q6
H
L H L Q0 ... Q6
H
H L L Q0 ... Q6
H
H H H Q0 ... Q6
H = high voltage level
L = low voltage level
X = don’t care
1