KK74LS138 Datasheet, PDF (1/4 Pages) KODENSHI KOREA CORP. – 3-to-8-Line Decoder/Demultiplexer

TECHNICAL DATA
3-to-8-Line Decoder/Demultiplexer
KK74LS138
This schottky-clamped TTL MSI circuit is designed to be used in
high-performance memory-decording or data-routing applications
requiring very short propagation delay time. In high-performance
memory systems this decode can be used to minimize the effects of
system decoding. When employed with high-speed memories utilizing a
fast enable circuit the delay times of this decorder and the enable time of
the memory are usually less than the typical access times of the memory.
This means that the effective system delay introduced by the schottky-
clampled system decoder is negligible.
• Designed Specifically for High Speed Memory Decoders and Data
Transmission Systems
• Incorporate 3 Enabler Inputs to Simplify Cascading AND/OR Data
Reception
• Schottky Clamped for High Performance
ORDERING INFORMATION
KK74LS138N Plastic
KK74LS138D SOIC
T_A = 0° to 70° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16 =V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
CS1CS2CS3 A2 A1A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXH
XHX
LXX
XXX
XXX
XXX
H H H HHHHH
H H H HHHHH
H H H HHHHH
HLL
HLL
HLL
HLL
LLL
LLH
LHL
LHH
L H H HHHHH
H L H HHHHH
H H L HHHHH
H H H LHHHH
HLL
HLL
HLL
HLL
HLL
HLH
HHL
HHH
H H H HLHHH
H H H HHLHH
H H H HHHLH
H H H HHHHL
H = high level (steady state)
L = low level (steady state)
X = don’t care
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