KK74HCT573A Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS

TECHNICAL DATA
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
KK74HCT573A
The KK74HCT573A is identical in pinout to the LS/ALS573. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High-Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are not
enabled.
• TTL/NMOS-Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
KK74HCT573AN Plastic
KK74HCT573ADW SOIC
T_A = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V_CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output
Output Latch D
Q
Enable Enable
L
H
H
H
L
H
L
L
L
L
X no change
H
X
X
Z
X = don’t care
Z = high impedance
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