KK74HCT109A Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Dual J-K Flip-Flop with set and Reset High-Performance Silicon-Gate CMOS

Dual J-K Flip-Flop
with set and Reset
High-Performance Silicon-Gate CMOS
TECHNICAL DATA
KK74HCT109A
The KK74HCT109A is identical in pinout to the LS/ALS109. The
KK74HCT109A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
This device consists of two J-K flip-flops with individual set, reset, and
clock inputs. Changes at the inputs are reflected at the outputs with the next
low-to-high transition of the clock. Both Q to Q outputs are available from
each flip-flop.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
KK74HCT109AN Plastic
KK74HCT109AD SOIC
T_A = -55° to 125° C for all packages.
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Output
Set Reset Clock J K Q Q
LH
X XX H L
HL
L
L
X XX L H
X
X X H^* H^*
HH
LL L H
HH
H L Toggle
HH
L H No Change
HH
HH H L
HH
L X X No Change
X = Don’t care
*_{Both outputs will remain high as long as Set and}
Reset are low., but the output states are
unpredictable if Set and Reset go high
simultaneously.
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