KK74HC573A Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Octal 3-State Noninverting Transparent Latch

TECHNICAL DATA
KK74HC573A
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
The KK74HC573A is identical in pinout to the LS/ALS573. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when LE is high. When LE goes low, data meeting the
setup and hold time becomes latched.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SOIC
ORDERING INFORMATION
KK74HC573AN
KK74HC573ADW
Plastic DIP
SOIC
T_A = -55° to 125° C for all packages
LOGIC DIAGRAM
DATA
INPUTS
D0 ²
D1 ³
D2 ⁴
D3 ⁵
D4 ⁶
D5 ⁷
D6 ⁸
D7 ⁹
19 _Q0
18 _Q1
17 _Q2
16 _Q3
15 _Q4
14 _Q5
13 _Q6
12 _Q7
NON INVERTING
OUTPUTS
PIN ASSIGNMENT
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 V _CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
11
LE
OE ¹
PIN 20=V_CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X no change
H
X
X
Z
H= high level
L = low level
X = don’t care
Z = high impedance
1