KK74HC175A Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Quad D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS

TECHNICAL DATA
Quad D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
KK74HC175A
The KK74HC175A is identical in pinout to the LS/ALS175. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is asynchronous
and occurs when a low level is applied to the Reset input. Information at a
D input is transferred to the corresponding Q output on the next positive-
going edge of the Clock input.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC175AN Plastic
KK74HC175AD SOIC
T_A = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Reset Clock D Q Q
L
X
X
LH
H
H HL
H
L
LH
H
L
X no change
X = Don’t care
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