KK74HC165A Datasheet, PDF (1/8 Pages) KODENSHI KOREA CORP. – 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS

TECHNICAL DATA
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The KK74HC165A is identical in pinout to the LS/ALS165. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs from
the last stage. Data may be loaded into the register either in parallel or in
serial form. When the Serial Shift/ Parallel Load input is low, the data is
loaded asynchronously in parallel. When the Serial Shift/Parallel Load
input is high, the data is loaded serially on the rising edge of either Clock
or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to act
as a clock inhibit.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
KK74HC165A
ORDERING INFORMATION
KK74HC165AN Plastic
KK74HC165AD SOIC
T_A = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16=V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Internal Stages Output
Serial Shift/ Clock Clock S A-H Q_A Q_B-Q_G Q_H
Parallel Load
Inhibit _A
L
H
X X a...h a
b-g
h
H
L LX
L
Q_An-Q_Fn Q_Gn
H
L HX
H
Q_An-Q_Fn
Q_Gn
H
L
H
L
LX
HX
L
Q_An-Q_Fn Q_Gn
H
Q_An-Q_Fn
Q_Gn
H
X
H XX
no change
H
H
X XX
H
L
L XX
X = Don’t Care
Q_An-Q_Fn = Data shifted from the preceding stage
no change
Operation
Asynchronous Parallel Load
Serial Shift via Clock
Serial Shift via Clock
Inhibit
Inhibited Clock
No Clock
1