KK74HC112A Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

TECHNICAL DATA
Dual J-K Flip-Flop
with Set and Reset
High-Performance Silicon-Gate CMOS
KK74HC112A
The KK74HC112A is identical in pinout to the LS/ALS112. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC112AN Plastic
KK74HC112AD SOIC
T_A = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K
Q
Q
L
H
X
XX H
L
H
L
L
L
X
XX L
H
X
XX
L^*
L^*
H
H
L L No Change
H
H
LH L
H
H
H
HL H
L
H
H
HH
Toggle
H
H
L
X X No Change
H
H
H
X X No Change
H
H
X X No Change
* Both output will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
1