KK74AC533 Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Octal 3-State Inverting Transparent Latch High-Speed Silicon-Gate CMOS

TECHNICAL DATA
Octal 3-State Inverting
Transparent Latch
High-Speed Silicon-Gate CMOS
KK74AC533
The KK74AC533 is identical in pinout to the LS/ALS533,
HC/HCT533. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears as the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are not
enabled.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
• 3-State Outputs for Bus Interfacing
ORDERING INFORMATION
KK74AC533N Plastic
KK74AC533DW SOIC
T_A = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V_CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output Latch D
Enable Enable
L
HH
L
HL
L
LX
H
XX
X = don’t care
Z = high impedance
Output
Q
L
H
no
change
Z
1