KK74AC373 Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

TECHNICAL DATA
Octal 3-State Noninverting
Transparent Latch
High-Speed Silicon-Gate CMOS
KK74AC373
The KK74AC373 is identical in pinout to the LS/ALS373,
HC/HCT373. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are not
enabled.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74AC373N Plastic
KK74AC373DW SOIC
T_A = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V_CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output Latch D
Enable Enable
L
H
H
L
H
L
L
L
X
H
X
X
X = Don’t Care
Z = High Impedance
Output
Q
H
L
No Change
Z
1