KK7472 Datasheet, PDF (1/5 Pages) KODENSHI KOREA CORP. – AND-Gated J-K Master-Slave Flip- Flops with Reset and Clear

AND-Gated J-K Master-Slave Flip-
Flops with Reset and Clear
LOGIC DIAGRAM
TECHNICAL DATA
KK7472
ORDERING INFORMATION
KK7472N Plastic
KK7472D SOIC
T_A = -10° to 70° C for all packages
PIN ASSIGNMENT
PIN 14 =V_CC
PIN 7 = GND
FUNCTION TABLE
NC - No internal connection
Inputs
Output
Reset Clear Clock J K Q Q
L
H
X XXH L
H
L
X XX L H
L
L
X
X X H^* H^*
H
H
L L Q₀ Q₀
H
H
HLH L
H
H
LHL H
H
H
H H TOGGLE
X =don’t care
Q₀ = the level of Q before the indicated input conditions were established.
TOGGLE: Each output changes to the complement of its previous level on each
active transition (pulse) of the clock.
*_{This configuration is nonstable; that is, it will not persist whenpreset and clear inputs}
return to their inactive (high) level.
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