KK4027B Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Dual JK Flip-Flop

TECHNICAL DATA
Dual JK Flip-Flop
KK4027B
The KK4027B is a Dual JK Flip-Flop which is edge-triggered and
features independent Set, Reset, and Clock inputs. Data is accepted when
the Clock is LOW and transferred to the output on the positive-going edge
of the Clock. The active HIGH asynchronous Reset and Set are
independent and override the J, K, or Clock inputs. The outputs are
buffered for best system performance.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4027BN Plastic
KK4027BD SOIC
T_A = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16 =V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q_n+1 Q_n+1
L H X XX L H
H L X XX H L
H H X XX H H
LL
L L No change
LL
HL H L
LL
LH L H
LL
H H Qn Qn
X = don’t care
Qn+1 = State After Clock Positive Transition
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