KK4021B Datasheet, PDF (1/5 Pages) KODENSHI KOREA CORP. – 8-Bit Shift Register High-Voltage Silicon-Gate CMOS

TECHNICAL DATA
KK4021B
8-Bit Shift Register
High-Voltage Silicon-Gate CMOS
The KK4021B is an Edge-Triggered 8-Bit Shift Register (Parallel-to-
Serial Converter) with a synchronous Serial Data Input (D_S), a Clock
Input (CP), an asynchronous active HIGH Parallel Load Input (PL), eight
asynchronous Parallel Data Inputs (P₀-P₇) and Buffered Parallel Outputs
from the last three stages (Q₅-Q₇).
Information on the Parallel Data Inputs (P0-P7) is asynchronously
loaded into the register while the Parallel Load Input (PL) is HIGH,
independent of the Clock (CP) and Serial Data (D_S) inputs. Data present
in the register is stored on the HIGH-to-LOW transition of the Parallel
Load Input (PL).
When the Parallel Load Input is LOW, data on the Serial Data Input
(D_S) is shifted into the first register position and all the data in the register
is shifted one position to the right on the LOW-to-HIGH transition of the
Clock Input (CP).
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4021BN Plastic
KK4021BDW SOIC
T_A = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V_CC
PIN 8 = GND
FUNCTION TABLE
SERIAL OPERATION:
t CP D_S PL
n
00
n+1
10
n+2
00
n+3
10
X0
Q₅
t=n+6
0
1
0
1
Q₅
Q₆
t=n+7
0
1
0
Q₆
Q₇
t=n+8
0
1
Q₇
PARALLEL OPERATION:
CP D_S PL P₅ P₆ P₇ Q₅ Q₆ Q₇
X X 1 DDDDDD
X = don’t care
D = 1 or 0
1