81133A Datasheet, PDF (7/10 Pages) Keysight Technologies – 3.35 GHz Pulse Pattern Generators

07 | Keysight | 81133A and 81134A, 3.35 GHz Pulse Pattern Generators - Data Sheet
Pulse Pattern and Data Functionality
The 81133A and 81134A can generate an 8 KBit digital pattern in
NRZ, RZ and R1 mode. Furthermore, the 81133A and 81134A can
provide a hardware generated pseudo random binary sequence
(PRBS) from 2⁵ - 1 to 2³¹ - 1.
Jitter Emulation (Delay Control Input)
Full control over the signal quality of pulse and data signals pro-
vides the Delay Control Input. With an external modulation source
(e.g. Keysight 33250A) the amount and shape of signal jitter can
be varied for stress tests or to emulate real world signals. The
external source for jitter modulation is applied to this input. Jitter
modulation can be turned on and off individually for each chan-
nel. Either one of two fixed sensitivities can be selected ± 25 ps
or ± 250 ps resulting in a total of 50 ps or 500 ps. The amplitude
of the modulated jitter is set by the voltage level of the signal
applied to the Delay Control Input. The Variable Crossover Point
feature provides additional control over the signal quality.
Data generation
Memory depth 8 Kbit per channel/12 Mbit extended memory
Data format
RZ/NRZ/R1
PRBS
2ⁿ-1 , n = 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 23, 31
PRBS
Polynomial
Comment
2⁵-1
X⁵ + X⁴ + X² + X¹ + 1
2⁶-1
X⁶ + X⁵ + X³ + X² + 1
ITU-T V.29
2⁷-1
X⁷ + X⁶ + 1
2⁸-1
X⁸ + X⁷ + X³ + X² + 1
2⁹-1
X⁹ + X⁵ + 1
CCITT 0.153/ITU-T V.52
2¹⁰-1
X¹⁰ + X⁷ + 1
CCITT 0.152/ITU-T 0.152
2¹¹-1
X¹¹ + X¹⁹ + 1
2¹²-1
X¹² + X⁹ + X⁸ + X⁵ + 1
2¹³-1
X¹³ + X¹² + X¹⁰ + X⁹ + 1
2¹⁴-1
X¹⁴ + X¹³ + X¹⁰ + X⁹ + 1
2¹⁵-1
X¹⁵ + X¹⁴ + 1
CCITT 0.151/ITU-T 0.151
2²³-1
X²³ + X¹⁸ + 1
CCITT 0.151/ITU-T 0.151
2³¹-1
X³¹ + X²⁸ + 1
Trigger output
Amplitude
Level window
Resolution
Format fixed duty cycle
Maximum external voltage
Transition times (20% to 80%
of amplitude)
Minimum output frequency
Mode clock clock divided by 1,2,3, . .
Disable
Delay control input
Interface
Impedance
Input levels for full modulation range
Max input levels
Delay modulation range
Modulation frequency
50 mV to 2.00 V
–2.00 V . . +3.00 V
10 mV
50% nominal
–2.00 V . . +3.00 V
< 100 ps (< 70 ps typical)
15 MHz/divider factor
2³¹-1 or trigger on bit 0 of data
Yes (relay)
dc-coupled
50 Ohm nominal
±500 mV
±2.5 V
±250 ps, ±25 ps, selectable
0 Hz - 200 MHz
Figure 2. Modulated Delay (Jitter) vs Voltage Level at Delay-Control-Input for
±250 ps and ±25 ps settings
33250A modulation
Jitter modulated