U5309A Datasheet, PDF (6/14 Pages) Keysight Technologies – PCIe High-Speed Digitizer with On-Board Processing

06 | Keysight | U5309A PCIe High-Speed Digitizer with On-Board Processing - Data Sheet
Firmware options
The U5309A PCIe high-speed digitizer provides several firmware
options:
–– DGT: Digitizer firmware
–– FDK¹: Custom firmware capablity
(required to load FPGA firmware created with U5340A)
–– AVG¹: Firmware for real-time sampling and averaging
–– PKD¹: Firmware for real-time signal peak detection
–– TSR¹: Firmware for triggered simultaneous acquisition and
readout.
Firmware
-DGT
-FDK
-AVG
-PKD
-TSR
Channel configuration
-CH2
-CH8
Sampling rate
Sampling rate
-SR0
-SR1
-SR2
-SR1
-
2
-
2
-
-
Table 1. Firmware options versus sampling rate.
FDK custom firmware capable
This option enables loading of custom firmware created with the
U5340A FPGA development kit.
AVG firmware for real-time sampling and averaging²
Synchronous real-time sampling and accumulation up to
2 GS/s on single-channel and 1 GS/s on dual-channel with:
–– Accumulation of 1 up to 520,000 triggers per record in steps of
8 triggers³.
–– Effective acquisition length of up to 480 KSamples in single
channel or 240 KSamples per channel in dual-channel.
–– Noise suppressed accumulation (NSA).
–– Self-trigger mode for minimal synchronous noise.
PKD firmware for real-time signal peak detection²
Synchronous real-time sampling and peak detection up to
2 GS/s on single-channel and 1 GS/s on dual-channel with:
–– Accumulation of 1 up to 520,000 triggers per record in steps of
8 triggers³.
–– Effective acquisition length of up to 480 KSamples in single
channel or 240 KSamples per channel in dual-channel.
Easy firmware switch
A simple call to the configuration function will enable to switch to
the required option.
DGT digitizer firmware
The digitizer firmware:
–– Allows standard data acquisition, including: digitizer
initialization, setting of the acquisition and clocking modes,
management of channel triggering for best synchronization,
storing data in the internal memory and/or transferring them
through the backplane bus.
–– Implements multi-record acquisition functionality.
–– Supports fixed internal clocking frequency with internal or
external reference, and variable frequency external clock.
–– Programmable binary decimation to lower the sample rate by
a factor of 2ⁿ where n is defined in the range of 1 to 10 (for
single record). e.g. for a U5309A-SR2 you can select from
2 GS/s down to 1.953125 MS/s.
–– Trigger time interpolator (TTI): high precision integrated
time to digital converter can be used to increase time
measurement accuracy.
TSR firmware for triggered simultaneous
acquisition and readout
The triggered simultaneous acquisition and readout concept
guarantees no lost triggers at high repetition rate for specific
configuration⁴:
–– Larger memory size increases the maximum margin for host PC
processing time, and allows for short to very long record size.
–– The architecture allows to continuously acquire new records
while reading previous ones.
–– PCIe 2.0 with 8 lanes allows fast data throughput.
–– High precision integrated time to digital converter can be used
to increase time measurement accuracy.
1.  A calibration digitizer function is available with each firmware.
2.  With the combination of -CH2 and -SR2 options, -AVG and -PKD are on one channel only.
3.  Expected for 8 first triggers.
4.  Please contact Keysight to find out the repetition rate that can be achieved in your application.