N4880A Datasheet, PDF (5/11 Pages) Keysight Technologies – Reference Clock Multiplier

05 | Keysight | N4880A Reference Clock Multiplier - Data Sheet
Application Example: MIPI M-PHY
MIPI M-PHY receiver test means to overcome several test challenges: this includes testing
of one or multiple lanes, support of multiple bit rates (so-called Gear 1, 2, 3 and 4), creating
pattern sequences to switch between the device states or switch into loopback mode, jitter
injection, emulating compliant channel conditions and handling different ways of error
counting.
For MIPI M-PHY receiver test on multiple lanes often a ParBERT 81250A setup is recom-
mended. To test HS Gear 4 devices, the N4880A can be used as shown in Figure 4. A low
frequency clock signal with multi-UI in-band jitter (SJ < f ) _{L_RX} is generated by a vector signal
generator. This can be multiplied by N4880A to be used as jittered high-speed external clock
for the ParBERT 13G clock module. This allows locking of ParBERT’s generator and analyzer
channels on this external clock signal. The N4880A can multiply from all MIPI M-PHY reference
clock rates of 19.2, 26, 38.4 and 52 MHz to all high-speed bit rates. However, to achieve lower
than HS Gear 4 bit rates the shown vector signal generator can send a high-speed clock itself.
Out-of-band jitter (SJ > f ) _{L_RX} and RJ can be generated in addition to the in-band jitter by
using ParBERT’s delay control inputs modulated by an arbitrary function noise generator such
as Keysight 81160A. A clean reference clock signal for the MIPI device can be generated by
ParBERT using a second clock group.
81160A
N5182A or E4438C
N4880A
ParBERT 81250A
81160A arbitrary function generator
81160A, N5182A or E4438C
vector signal generator
ParBERT
Ext. clock
E4809A 13.5G clock
Delay ctrl in
E4872A 13G generator
E4808A 10.8G clock
Delay ctrl in
E4862B 3.35G generator
E4862B 3.35G generator
E4809A 13.5G clock
N4873A 13G analyzer
(or other error counting)
500 ps SJ+RJ
200 ps RJ
38.4 or 52 MHz clock
N4880A ref clock multiplier
Clock with
SJ > f_{L_RX}
Channel
Clock with
SJ > f_{L_RX}
DUT: MIPI M-PHY receiver
M-RX Loop
back
M-TX
Error
Ctr
19.2/ 26/ 38.4/ 52 MHz
clean reference clock
Figure 4. This shows a MIPI M-PHY receiver test setup with the N4880A, ParBERT 81250A and two stress generators. The example shows a HS Gear 4
setup for testing one receiver lane for M-PHY data rates of 9.984, 11.648, or 11.6736 Gb/s.