W2324EP Datasheet, PDF (3/4 Pages) Keysight Technologies – Layout Pre-processor Element

03 | Keysight | EEsof EDA W2324 High Capacity Layout Pre-processor Element - Data Sheet
First, the signal integrity engineer combines vendor IC models with a pre-layout “placeholder” for the
channel. Typically this placeholder is created from the ADS Multi-Layer Models (MLM) transmission line
library possibly supplemented with EM-based via models. The goal of the pre-layout simulation batches is to
explore the design space and optimize IC settings (such as the transmitter (Tx) SERDES pre-emphasis filter
taps and the receiver (Rx) SERDES equalizer taps and clock/data recovery (CDR) circuit settings), stack up,
controlled impedance line geometry, and via design.
These parameters are given to the physical designer to load into the Constraint Editor of the auto-router
of a third-party enterprise PCB tool such as Expedition from Mentor Graphics. Once the board is routed,
post-layout artwork is available in ODB++ file format.
Figure 2.
One of several critical nets is highlighted in cyan. Note
that this very large PCB has been “cookie cut,” with
the left hand edge being a convex hull that includes
this leftmost net and a margin around it.
The signal integrity engineer selects the critical nets and pre-processes the important section of the PCB
for EM modeling. The resulting EM model is used to “swap out” the pre-layout placeholder with the
characteristics of the actual post-layout design. In this way the candidate layout can be verified before
manufacturing. If the candidate design has issues such as excessive crosstalk, the signal integrity engineer
can adjust the critical area in the ADS Layout “sandbox” (for example by added stitching vias or guard traces)
and solve the new candidate until a satisfactory adjustment is proven in. The physical designer then applies
the knowledge from the ADS experimentation to the “golden” copy of the design in the third-party enterprise
PCB tool for first pass success. This methodology avoids the expensive, time consuming, and
non-deterministic “cut and try” approach to qualifying the post-layout, namely serial fabrication and
measurement of multiple prototypes.