W2317EP Datasheet, PDF (3/4 Pages) Keysight Technologies – Bus Simulator

03 | Keysight | W2309EP/ET DDR Bus Simulator and W2317EP/ET DDR Bus Simulator Distributed Computing 8-pack - Data Sheet
Speed Up Simulation Time
Individual simulations are fast so designers can run in batch mode to quickly explore the
design space. An additional product, the W2317EP/ET DDR Bus Simulator Distributed
Computing 8-pack, enables you to farm out parameter sweeps to a compute cluster.
Figure 2. DDR batch simulation.
Rigorous DQ and DQS Eye Calculations
The DDR Bus Simulator offers rigorous DQ (DDR Data Input/Output) and DQS (DDR
Data Strobe) eye calculations to arbitrarily low BER levels, including the 1E-16 contour
speciied by JEDEC, accounting for crosstalk and for asymmetry between rising and
falling transition times. It provides comprehensive timing and voltage margins between
the selected BER contour and the DDR4 receive mask speciication.
Figure 3. The built-in transmitter includes an optional
pre-emphasis.
Mix-and-Match between Built-in, IBIS and Circuit
Models
The product allows for three IC model types: built-in, Input/output Buffer Information
Speciication (IBIS), or circuit models. The built-in driver and receiver model de-emphasis
and continuous-time linear equalization (CTLE), respectively. Designers can “mix-and-
match” model types in their schematic.
Figure 4. The built-in receiver includes CTLE capability.