U4321A Datasheet, PDF (3/12 Pages) Keysight Technologies – PCI Express® 3.0 Analyzer Module

Overview
Product description
Keysight Technologies’ high speed U4301A PCI Express^®
3.0 analyzer module is a protocol analyzer supporting all
PCI Express^® applications from Gen1 through Gen3 and
speeds, including 2.5 GT/s (Gen1) and 5.0 GT/s (Gen2)
through PCIe 8 GT/s (Gen3) and with link widths from x1
to x16. The U4301A analyzer captures and decodes PCI
Express data and displays it in a packet viewer window.
The U4301A analyzer is a blade that is installed in an AXIe
two slot M9502A or five slot M9505A.
Probing is provided by the U4321A solid slot interposer
probe, U4324A flying lead solder down probe, or the
U4322A mid bus probe based on Keysight’s equalization
snoop probe (ESP) technology.
Stimulus and response testing of the PCIe system is
accomplished with the addition of the U4305A PCIe Gen3
exerciser.
A link training status state machine (LTSSM) exerciser
provides stimulus for testing PCIe links up to the full
speed of Gen3 systems. The analyzer LTSSM overview can
pinpoint specific training sequence issues through easy to
interpret analysis results.
Keysight’s Transactional decoder includes a transactional
viewer that allows the designer to select transactional
queues and performance information from the analyzer’s
NVMe transaction overview pane. This organizes the
transactions by direction or by queue to follow the data
flow across the interface, with one-click control. Individual
PRP (Physical Region Page) lists contain all of the key
information of the NVMe queues, allowing designers to
quickly review and validate the data flows over the PCIe
connections.
The Performance analysis package includes the real data
throughput calculations, with response-time measurement
of the PCIe data flow. It allows designers to measure and
understand throughput performance, PCIe response times,
and other operational measurements that provide the
insight needed to optimize device performance.
Analysis
and debug
Industry
leading probes
Stimulus and test
U4305A exerciser
–– Support for Gen1 through Gen3, x1
through x16 link width
–– 4 GB of capture buffer per module
–– Non-intrusive probing that leverages
ESP technology
–– The mid-bus probe supports x1
to x16 unidirectional or x1 to x8
bidirectional
–– The solid slot interposer will support
x1 to x16 unidirectional or bidirec-
tional
–– The flying lead solder down probe
offers support for x1 & x2 bidirec-
tional capability on a single probe.
Other standard lane width configu-
ration support is x4, x8, & x16
–– Support for Gen1 through Gen3 and
link widths of x1 through x16
–– Link testing from x1 through x16,
using automated LTSSM exerciser
–– PCIe, MR-IOV, and SR-IOV stimulus
response testing
–– INVMe Root Complex emulation
for test and verification of NVMe
devices
–– Protocol test card (PTC) to measure
PCIe Gen3 DUT port and system
BIOS specification compliance as
defined by the PCI SIG standards
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